In the manufacture of integrated circuits,
it is often necessary to coat silicon wafers with photoresist for later
lithographic imaging. To learn more about a specific resist, an experiment was
run to determine the effects of several factors on the photoresist coating
process. The three most important factors were thought to be development time,
prebake temperature, and post-exposure bake temperature. Based on current
theories, the scientists thought that the single most important factor would be
development time—this was thought to increase the Gamma value (explained
below), but in a non-linear way. The second most important factor was expected
to be pre-bake, and the third most important factor was thought to be
Note to students: you do not need to understand the technical details of
this process to answer the THE questions!
Three responses were measured:
Gamma (“Gamma”). A measure of
how fast the resist will clear. A higher gamma refers to a sharper image and
this is desired. This is the most important response.
Dose to clear (“DTC”). Amount
of energy needed to expose the resist that will develop away cleanly. Minimum
amount is desired. This is the second most important response.
Thickness loss (“ThkLoss”).
This is a loss of photoresist after development. Minimal loss is desired. This
is third most important response.
The factors levels were
Development time (“DevTime”).
37, 45 (standard), 53, and 61 seconds.
(“PreBake”). 100 (standard) and 110 C.
Post-Exposure bake (“PEB”). 110
(standard) and 120 C.
All combinations were run twice. The
experiment was run in a completely random order, over a one-day period. One
wafer was used per run, so 32 wafers were used in all. The wafers were selected
at random from a set of wafers that were available for the experiment. The
wafer # is the same as the time order—for example, Wafer #1 was run first, and
Wafer #32 was run last.
The Treatment Structure is: 4x2x2 factorial
Error-Control Structure is: Completely Randomized
Design, with 2 replicates
extended structure diagram is:
Where DT = DevTime, Fixed with 4 treat
levels, Pr = PreBake, Fixed with 2 Treat levels, and PE = Post Bake, Fixed with
2 treat levels, and R = Wafers, Random Experimental Units
the error-control structure by explaining a simple way to create a
better error-control structure (without using any
additional resources). Show the
structure diagram for this improved design. (Of
course, the experiment was
already run, so it is too late to change the design!
What I want you to think about
is how you would have improved the design while the
design was still being